869 search results - page 139 / 174 » Cache Architectures for Reconfigurable Hardware |
ERSA
2006
13 years 9 months ago
2006
- In this paper, we present a prototype FPGA design for an efficient physical layer implementation of a MIMO-OFDM technique. We propose a pipelined architecture using a Fast Fourie...
ISCA
2012
IEEE
11 years 10 months ago
2012
IEEE
The emergence of global-scale online services has galvanized scale-out software, characterized by splitting vast datasets and massive computation across many independent servers. ...
CAV
2003
Springer
14 years 24 days ago
2003
Springer
Many verification problems reduce to proving the validity of formulas involving both propositional connectives and domain-specific functions and predicates. This paper presents ...
ISCA
2010
IEEE
14 years 19 days ago
2010
IEEE
DRAM vendors have traditionally optimized the cost-perbit metric, often making design decisions that incur energy penalties. A prime example is the overfetch feature in DRAM, wher...
HPCA
2011
IEEE
12 years 11 months ago
2011
IEEE
Future CMPs will combine many simple cores with deep cache hierarchies. With more cores, cache resources per core are fewer, and must be shared carefully to avoid poor utilization...