869 search results - page 154 / 174 » Cache Architectures for Reconfigurable Hardware |
IPPS
2000
IEEE
13 years 12 months ago
2000
IEEE
The Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus) is a low-latency, high-bandwidth interconnection network which directly links arbitrary pairs of processor nodes wit...
ICPADS
1998
IEEE
13 years 11 months ago
1998
IEEE
Java-Web Computing paradigm changed Internet into computing environment. For Java-Web Computing and many Java applications, a new Java processor, called simultaneous multithreaded...
DAC
1999
ACM
14 years 8 months ago
1999
ACM
This paper presents a methodology for cycle-accurate simulation of energy dissipation in embedded systems. The ARM Ltd. 1 instruction-level cycle-accurate simulator is extended wi...
ISPAN
2008
IEEE
14 years 1 months ago
2008
IEEE
Data prefetching has been considered an effective way to mask data access latency caused by cache misses and to bridge the performance gap between processor and memory. With hardw...
PDIS
1991
IEEE
13 years 11 months ago
1991
IEEE
Improvements in the processing speed of multiprocessors are outpacing improvements in the speed of disk hardware. Parallel disk I/O subsystems have been proposed as one way to clo...