869 search results - page 163 / 174 » Cache Architectures for Reconfigurable Hardware |
HPCA
1998
IEEE
13 years 11 months ago
1998
IEEE
The performance of a concurrent multithreaded architectural model, called superthreading 15 , is studied in this paper. It tries to integrate optimizing compilation techniques and...
WMPI
2004
ACM
14 years 27 days ago
2004
ACM
High-performance out-of-order processors spend a significant portion of their execution time on the incorrect program path even though they employ aggressive branch prediction al...
SIGGRAPH
1998
ACM
13 years 11 months ago
1998
ACM
We describe the clipmap, a dynamic texture representation that efficiently caches textures of arbitrarily large size in a finite amount of physical memory for rendering at real-...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
In this paper we present a methodology that is based on SystemC [1] for rapid prototyping to greatly enhance and accelerate the exploration of complex systems to optimize the syst...
FPGA
1995
ACM
13 years 11 months ago
1995
ACM
During the development of computer peripherals which interface to the processor via the system bus it is often necessary to acquire the signals on the bus at the hardware level. I...