869 search results - page 74 / 174 » Cache Architectures for Reconfigurable Hardware |
KES
2008
Springer
13 years 10 months ago
2008
Springer
This paper introduces the Perplexus hardware platform, a scalable computing substrate made of custom reconfigurable devices endowed with bio-inspired capabilities. This platform w...
VLSISP
2008
13 years 10 months ago
2008
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications whic...
ISCA
1995
IEEE
14 years 1 months ago
1995
IEEE
Current trends in processor design are pointing to deeper and wider pipelines and superscalar architectures. The efficient use of these resources requires speculative execution, ...
ERSA
2008
13 years 11 months ago
2008
- This paper presents a framework that improves the portability and ease-of-use issues of current Reconfigurable Computers (RCs). These two drawbacks should be solved in order for ...
ICCAD
2002
IEEE
14 years 7 months ago
2002
IEEE
Embedded system programs tend to spend much time in small loops. Introducing a very small loop cache into the instruction memory hierarchy has thus been shown to substantially red...