869 search results - page 75 / 174 » Cache Architectures for Reconfigurable Hardware |
DSD
2008
IEEE
13 years 12 months ago
2008
IEEE
Caching mechanism has achieved great success in general purpose processor; however, its deployment in Network Processor (NP) raises questions over its effectiveness under the new ...
FPL
1998
Springer
14 years 2 months ago
1998
Springer
This paper discusses the memory interface of custom computing machines. We present a high speed parallel memory for the MoM-PDA machine, which is based on the Xputer paradigm. The ...
IEEEHPCS
2010
13 years 4 months ago
2010
Network Multimedia data also need to be encrypted to protect private content and access control. Considering performance constraints and embedded system issues, many hardware solu...
ISCA
1994
IEEE
14 years 2 months ago
1994
IEEE
In the near future, semiconductor technology will allow the integration of multiple processors on a chip or multichipmodule (MCM). In this paper we investigate the architecture an...
WMPI
2004
ACM
14 years 3 months ago
2004
ACM
Clustered microarchitectures are an effective organization to deal with the problem of wire delays and complexity by partitioning some of the processor resources. The organization ...