54 search results - page 5 / 11 » Cache Based Remote Timing Attack on the AES |
CHES
2009
Springer
14 years 8 months ago
2009
Springer
We present a bitsliced implementation of AES encryption in counter mode for 64-bit Intel processors. Running at 7.59 cycles/byte on a Core 2, it is up to 25% faster than previous i...
ADBIS
2009
Springer
14 years 2 months ago
2009
Springer
Abstract. Caching data reduces user-perceived latency and often enhances availability in case of server crashes or network failures. DB caching aims at local processing of declarat...
CHES
2007
Springer
14 years 1 months ago
2007
Springer
Abstract. This paper discusses the state-of-the-art fast software implementation of block ciphers on Intel’s new microprocessor Core2, particularly concentrating on “bitslice i...
FSE
2006
Springer
13 years 11 months ago
2006
Springer
This paper studies the state-of-the-art software optimization methodology for symmetric cryptographic primitives on the new 64-bit x64 processors, AMD Athlon64 (AMD64) and Intel Pe...
SP
2009
IEEE
14 years 2 months ago
2009
IEEE
—This paper studies and evaluates the extent to which automated compiler techniques can defend against timing-based side-channel attacks on modern x86 processors. We study how mo...