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ICCL
1990
IEEE
13 years 11 months ago
Cache Performance of Combinator Graph Reduction
Philip J. Koopman Jr., Peter Lee, Daniel P. Siewio...
DATE
2010
IEEE
180views Hardware» more  DATE 2010»
14 years 21 days ago
A reconfigurable cache memory with heterogeneous banks
Abstract— The optimal size of a large on-chip cache can be different for different programs: at some point, the reduction of cache misses achieved when increasing cache size hits...
Domingo Benitez, Juan C. Moure, Dolores Rexachs, E...
ISPASS
2009
IEEE
14 years 2 months ago
Accurately approximating superscalar processor performance from traces
Trace-driven simulation of superscalar processors is particularly complicated. The dynamic nature of superscalar processors combined with the static nature of traces can lead to l...
Kiyeon Lee, Shayne Evans, Sangyeun Cho
ICDCS
1999
IEEE
13 years 12 months ago
Proxy Cache Coherency and Replacement - Towards a More Complete Picture
This work studies the interaction of Web proxy cache coherency and replacement policies using trace-driven simulations. We specifically examine the relative importance of each typ...
Balachander Krishnamurthy, Craig E. Wills
SIGIR
2008
ACM
13 years 6 months ago
ResIn: a combination of results caching and index pruning for high-performance web search engines
Results caching is an efficient technique for reducing the query processing load, hence it is commonly used in real search engines. This technique, however, bounds the maximum hit...
Gleb Skobeltsyn, Flavio Junqueira, Vassilis Placho...