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» Cache Performance of Combinator Graph Reduction
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TC
1998
13 years 7 months ago
Optimizing the Instruction Cache Performance of the Operating System
—High instruction cache hit rates are key to high performance. One known technique to improve the hit rate of caches is to minimize cache interference by improving the layout of ...
Josep Torrellas, Chun Xia, Russell L. Daigle
PVLDB
2008
167views more  PVLDB 2008»
13 years 6 months ago
Keyword search on external memory data graphs
Keyword search on graph structured data has attracted a lot of attention in recent years. Graphs are a natural "lowest common denominator" representation which can combi...
Bhavana Bharat Dalvi, Meghana Kshirsagar, S. Sudar...
ECRTS
2008
IEEE
14 years 2 months ago
WCET-driven Cache-based Procedure Positioning Optimizations
Procedure Positioning is a well known compiler optimization aiming at the improvement of the instruction cache behavior. A contiguous mapping of procedures calling each other freq...
Paul Lokuciejewski, Heiko Falk, Peter Marwedel
HIPC
1999
Springer
13 years 12 months ago
Microcaches
We describe a radically new cache architecture and demonstrate that it offers a huge reduction in cache cost, size and power consumption whilst maintaining performance on a wide ra...
David May, Dan Page, James Irwin, Henk L. Muller
PARA
2004
Springer
14 years 1 months ago
Speeding up Parallel Graph Coloring
Abstract. This paper presents new efficient parallel algorithms for finding approximate solutions to graph coloring problems. We consider an existing shared memory parallel graph...
Assefaw Hadish Gebremedhin, Fredrik Manne, Tom Woo...