286 search results - page 18 / 58 » Cache Remapping to Improve the Performance of Tiled Algorith... |
PLDI
2010
ACM
14 years 1 months ago
2010
ACM
This paper presents a novel optimizing compiler for general purpose computation on graphics processing units (GPGPU). It addresses two major challenges of developing high performa...
DSD
2010
IEEE
13 years 8 months ago
2010
IEEE
Abstract—Resizable caches can trade-off capacity for access speed to dynamically match the needs of the workload. In Simultaneous Multi-Threaded (SMT) cores, the caching needs ca...
TC
2008
13 years 8 months ago
2008
While many block replacement algorithms for buffer caches have been proposed to address the wellknown drawbacks of the LRU algorithm, they are not robust and cannot maintain a cons...
TC
1998
13 years 8 months ago
1998
—High instruction cache hit rates are key to high performance. One known technique to improve the hit rate of caches is to minimize cache interference by improving the layout of ...
WSC
2004
13 years 9 months ago
2004
In time-parallel simulation, the simulation time axis is decomposed into a number of slices which are assigned to parallel processes for concurrent simulation. Although a promisin...