286 search results - page 41 / 58 » Cache Remapping to Improve the Performance of Tiled Algorith... |
ISCA
2011
IEEE
13 years 4 days ago
2011
IEEE
Today’s chip-level multiprocessors (CMPs) feature up to a hundred discrete cores, and with increasing levels of integration, CMPs with hundreds of cores, cache tiles, and specia...
ICDCS
2008
IEEE
14 years 2 months ago
2008
IEEE
The multi-level storage architecture has been widely adopted in servers and data centers. However, while prefetching has been shown as a crucial technique to exploit the sequentia...
ICPP
2006
IEEE
14 years 2 months ago
2006
IEEE
— This paper presents a parallel external-memory algorithm for performing a breadth-first traversal of an implicit graph on a cluster of workstations. The algorithm is a paralle...
ASPLOS
1994
ACM
14 years 16 days ago
1994
ACM
Several researchers have proposed algorithms for basic block reordering. We call these branch alignment algorithms. The primary emphasis of these algorithms has been on improving ...
IEEEPACT
1999
IEEE
14 years 22 days ago
1999
IEEE
Image processing applications tend to access their data non-sequentially and reuse that data infrequently. As a result, they tend to perform poorly on conventional memory systems ...