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DSD
2010
IEEE
172views Hardware» more  DSD 2010»
13 years 7 months ago
Adaptive Cache Memories for SMT Processors
Abstract—Resizable caches can trade-off capacity for access speed to dynamically match the needs of the workload. In Simultaneous Multi-Threaded (SMT) cores, the caching needs ca...
Sonia López, Oscar Garnica, David H. Albone...
INFOCOM
2002
IEEE
14 years 14 days ago
Using the Small-World Model to Improve Freenet Performance
– Efficient data retrieval in a peer-to-peer system like Freenet is a challenging problem. In this paper we study the impact of cache replacement policy on the performance of Fre...
Hui Zhang 0002, Ashish Goel, Ramesh Govindan
ICMCS
2005
IEEE
80views Multimedia» more  ICMCS 2005»
14 years 1 months ago
Maximizing the profit for cache replacement in a transcoding proxy
Recent technology advances in multimedia communication have ushered in a new era of personal communication. Users can ubiquitously access the Internet via various mobile devices. ...
Hao-Ping Hung, Ming-Syan Chen
HPCA
2009
IEEE
14 years 8 months ago
A novel architecture of the 3D stacked MRAM L2 cache for CMPs
Magnetic Random Access Memory (MRAM) is considered to be a promising future memory technology due to its low leakage power, high density and fast read speed. The heterogeneous int...
Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yira...
ACMMSP
2006
ACM
247views Hardware» more  ACMMSP 2006»
14 years 1 months ago
A flexible data to L2 cache mapping approach for future multicore processors
This paper proposes and studies a distributed L2 cache management approach through page-level data to cache slice mapping in a future processor chip comprising many cores. L2 cach...
Lei Jin, Hyunjin Lee, Sangyeun Cho