26 search results - page 4 / 6 » Cache leakage control mechanism for hard real-time systems |
IPPS
1999
IEEE
13 years 11 months ago
1999
IEEE
Cooperative caches offer huge amounts of caching memory that is not always used as well as it could be. We might find blocks in the cache that have not been requested for many hou...
DAC
2010
ACM
13 years 7 months ago
2010
ACM
The performance of most embedded systems is critically dependent on the average memory access latency. Improving the cache hit rate can have significant positive impact on the per...
CF
2009
ACM
14 years 1 months ago
2009
ACM
Chip Multiprocessor (CMP) memory systems suffer from the effects of destructive thread interference. This interference reduces performance predictability because it depends heavil...
IEEEARES
2010
IEEE
14 years 11 days ago
2010
IEEE
—Monitoring a process and its file I/O behaviors is important for security inspection for a data center server against intrusions, malware infection and information leakage. In ...
ECRTS
2010
IEEE
13 years 8 months ago
2010
IEEE
Embedded control systems with hard real-time constraints require that deadlines are met at all times or the system may malfunction with potentially catastrophic consequences. Sched...