Sciweavers

31 search results - page 5 / 7
» Cache organizations for clustered microarchitectures
Sort
View
ICPADS
2006
IEEE
14 years 2 months ago
Oriented Overlays For Clustering Client Requests To Data-Centric Network Services
Many of the data-centric network services deployed today hold massive volumes of data at their origin websites, and access the data to dynamically generate responses to user reque...
Congchun He, Vijay Karamcheti
ASAP
2008
IEEE
142views Hardware» more  ASAP 2008»
14 years 3 months ago
Managing multi-core soft-error reliability through utility-driven cross domain optimization
As semiconductor processing technology continues to scale down, managing reliability becomes an increasingly difficult challenge in high-performance microprocessor design. Transie...
Wangyuan Zhang, Tao Li
LCTRTS
2009
Springer
14 years 3 months ago
Addressing the challenges of DBT for the ARM architecture
Dynamic binary translation (DBT) can provide security, virtualization, resource management and other desirable services to embedded systems. Although DBT has many benefits, its r...
Ryan W. Moore, José Baiocchi, Bruce R. Chil...
PLDI
1999
ACM
14 years 26 days ago
Cache-Conscious Structure Layout
Hardware trends have produced an increasing disparity between processor speeds and memory access times. While a variety of techniques for tolerating or reducing memory latency hav...
Trishul M. Chilimbi, Mark D. Hill, James R. Larus
ISPASS
2005
IEEE
14 years 2 months ago
Measuring Program Similarity: Experiments with SPEC CPU Benchmark Suites
Performance evaluation using only a subset of programs from a benchmark suite is commonplace in computer architecture research. This is especially true during early design space e...
Aashish Phansalkar, Ajay Joshi, Lieven Eeckhout, L...