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RTAS
2008
IEEE
14 years 3 months ago
WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches
Multi-core chips have been increasingly adopted by microprocessor industry. For real-time systems to safely harness the potential of multi-core computing, designers must be able t...
Jun Yan, Wei Zhang
ICMCS
2005
IEEE
80views Multimedia» more  ICMCS 2005»
14 years 2 months ago
Dynamic Server Redirect for Multimedia Service in Distributed Peer-to-Peer Network
Peer-to-Peer (P2P) multimedia application is expected to be one of the most important services supported by the next generation networks. However, how to balance server load in re...
Ming-Ho Hsiao, Suh-Yin Lee
JEC
2006
71views more  JEC 2006»
13 years 9 months ago
Destructive-read in embedded DRAM, impact on power consumption
This paper explores power consumption for destructive-read embedded DRAM. Destructive-read DRAM is based on conventional DRAM design, but with sense amplifiers optimized for lower ...
Haakon Dybdahl, Per Gunnar Kjeldsberg, Marius Gran...
PVLDB
2010
147views more  PVLDB 2010»
13 years 7 months ago
HYRISE - A Main Memory Hybrid Storage Engine
In this paper, we describe a main memory hybrid database system called HYRISE, which automatically partitions tables into vertical partitions of varying widths depending on how th...
Martin Grund, Jens Krüger, Hasso Plattner, Al...
CODES
2010
IEEE
13 years 7 months ago
Dynamic, non-linear cache architecture for power-sensitive mobile processors
Today, mobile smartphones are expected to be able to run the same complex, algorithm-heavy, memory-intensive applications that were originally designed and coded for generalpurpos...
Garo Bournoutian, Alex Orailoglu