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ICS
2004
Tsinghua U.
14 years 1 months ago
Effective stream-based and execution-based data prefetching
With processor speeds continuing to outpace the memory subsystem, cache missing memory operations continue to become increasingly important to application performance. In response...
Sorin Iacobovici, Lawrence Spracklen, Sudarshan Ka...
LCTRTS
2007
Springer
14 years 2 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...
ERLANG
2003
ACM
14 years 1 months ago
A study of Erlang ETS table implementations and performance
The viability of implementing an in-memory database, Erlang ETS, using a relatively-new data structure, called a Judy array, was studied by comparing the performance of ETS tables...
Scott Lystig Fritchie
ANCS
2009
ACM
13 years 6 months ago
Design and performance analysis of a DRAM-based statistics counter array architecture
The problem of maintaining efficiently a large number (say millions) of statistics counters that need to be updated at very high speeds (e.g. 40 Gb/s) has received considerable re...
Haiquan (Chuck) Zhao, Hao Wang, Bill Lin, Jun (Jim...
PCM
2004
Springer
112views Multimedia» more  PCM 2004»
14 years 1 months ago
A Study on the Quantization Scheme in H.264/AVC and Its Application to Rate Control
Compared with previous video coding standards, H.264/AVC employs a division-free quantization scheme. The relation between quantization parameter and quantization step changes from...
Siwei Ma, Wen Gao, Debin Zhao, Yan Lu