Addressing instruction fetch bottlenecks by using an instruction register file

The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by packing an application’s instructions, resulting in decreased code size, reduced energy consumption and improved execution time primarily due to a smaller footprint in the instruction cache. The nature of the IRF also allows the execution of packed instructions to overlap with instruction fetch, thus providing a means for tolerating increased fetch latencies, like those experienced by encrypted ICs as well as the presence of low-power L0 caches. Although previous research has focused on the direct benefits of instruction packing, this paper explores the use of increased fetch bandwidth provided by packed instructions. Small L0 caches improve energy efficiency but can increase execution time due to frequent cache misses. We show that this penalty can be significantly reduced by overlapping the execution o...

• Type: Conference
• Year: 2007
• Where: LCTRTS
• Authors: Stephen Roderick Hines, Gary S. Tyson, David B. Whalley
• Keywords: Instruction, Instruction Register File, LCTRTS 2007, Packed Instructions, Software Engineering