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ECRTS
2006
IEEE
14 years 2 months ago
WCET-Centric Software-controlled Instruction Caches for Hard Real-Time Systems
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...
Isabelle Puaut
FPGA
2000
ACM
122views FPGA» more  FPGA 2000»
14 years 9 days ago
A reconfigurable multi-function computing cache architecture
A considerable portion of a chip is dedicated to a cache memory in a modern microprocessor chip. However, some applications may not actively need all the cache storage, especially...
Huesung Kim, Arun K. Somani, Akhilesh Tyagi
LCTRTS
2005
Springer
14 years 2 months ago
A sample-based cache mapping scheme
Applications running on the StrongARM SA-1110 or XScale processor cores can specify cache mapping for each virtual page to achieve better cache utilization. In this work, we descr...
Rong Xu, Zhiyuan Li
DATE
2005
IEEE
133views Hardware» more  DATE 2005»
14 years 2 months ago
Compiler-Based Approach for Exploiting Scratch-Pad in Presence of Irregular Array Access
Scratch-pad memory is becoming an important fixture in embedded multimedia systems. It is significantly more efficient than the cache, in performance and power, and has the add...
Mohammed Javed Absar, Francky Catthoor
CGO
2006
IEEE
14 years 2 months ago
Thread-Shared Software Code Caches
Software code caches are increasingly being used to amortize the runtime overhead of dynamic optimizers, simulators, emulators, dynamic translators, dynamic compilers, and other t...
Derek Bruening, Vladimir Kiriansky, Timothy Garnet...