Configurable on chip multiprocessor systems combine advantages of task-level parallelism and the flexibility of field-programmable devices to customize architectures for paralle...
Harold Ishebabi, Philipp Mahr, Christophe Bobda, M...
In an intelligent memory architecture, the main memory of a computer is enhanced with many simple processors. The result is a highly-parallel, heterogeneous machine that is able t...
Basilio B. Fraguela, Jose Renau, Paul Feautrier, D...
We present Chorus, a high-level parallel programming model suitable for irregular, heap-manipulating applications like mesh refinement and epidemic simulations, and JChorus, an i...
Roberto Lublinerman, Swarat Chaudhuri, Pavol Cern&...
Advances in massively parallel platforms are increasing the prospects for high performance discrete event simulation. Still the di culty in parallel programming persists and there...
We demonstrate the bene ts of instruction-set simulation in the evaluation of a parallel programming system, Penny. The simulator is a reliable tool in exploring design alternativ...