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ISCA
1997
IEEE
120views Hardware» more  ISCA 1997»
13 years 11 months ago
Run-Time Adaptive Cache Hierarchy Management via Reference Analysis
Improvements in main memory speeds have not kept pace with increasing processor clock frequency and improved exploitation of instruction-level parallelism. Consequently, the gap b...
Teresa L. Johnson, Wen-mei W. Hwu
MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
13 years 5 months ago
Throughput-Effective On-Chip Networks for Manycore Accelerators
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
Ali Bakhoda, John Kim, Tor M. Aamodt
ICDCS
2011
IEEE
12 years 7 months ago
Intelligent Placement of Datacenters for Internet Services
—Popular Internet services are hosted by multiple geographically distributed datacenters. The location of the datacenters has a direct impact on the services’ response times, c...
Iñigo Goiri, Kien Le, Jordi Guitart, Jordi ...
CIDR
2009
98views Algorithms» more  CIDR 2009»
13 years 8 months ago
From Declarative Languages to Declarative Processing in Computer Games
Recent work has shown that we can dramatically improve the performance of computer games and simulations through declarative processing: Character AI can be written in an imperati...
Ben Sowell, Alan J. Demers, Johannes Gehrke, Nitin...
IEEEPACT
2007
IEEE
14 years 1 months ago
Architectural Support for the Stream Execution Model on General-Purpose Processors
There has recently been much interest in stream processing, both in industry (e.g., Cell, NVIDIA G80, ATI R580) and academia (e.g., Stanford Merrimac, MIT RAW), with stream progra...
Jayanth Gummaraju, Mattan Erez, Joel Coburn, Mende...