For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the desig...
Todd M. Austin, Dionisios N. Pnevmatikatos, Gurind...
Recent studies have shown that in highly associative caches, the performance gap between the Least Recently Used (LRU) and the theoretical optimal replacement algorithms is large,...
Memory performance is increasingly determining microprocessor performance and technology trends are exacerbating this problem. Most architectures use set-associative caches with L...
Zhenlin Wang, Kathryn S. McKinley, Arnold L. Rosen...
Persistent programming languages manage volatile memory as a cache for stable storage, imposing a read barrier on operations that access the cache, and a write barrier on updates ...
Antony L. Hosking, Nathaniel Nystrom, Quintin I. C...
Data persistency is a fundamental, but complex aspect of a modern software development process. Therefore, in order to reduce development costs and improve a system’s quality, s...
Gernot Schmoelzer, Stefan Mitterdorfer, Christian ...