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ISCA
1996
IEEE
126views Hardware» more  ISCA 1996»
13 years 11 months ago
Memory Bandwidth Limitations of Future Microprocessors
This paper makes the case that pin bandwidth will be a critical consideration for future microprocessors. We show that many of the techniques used to tolerate growing memory laten...
Doug Burger, James R. Goodman, Alain Kägi
VLDB
2004
ACM
143views Database» more  VLDB 2004»
14 years 28 days ago
Clotho: Decoupling memory page layout from storage organization
As database application performance depends on the utilization of the memory hierarchy, smart data placement plays a central role in increasing locality and in improving memory ut...
Minglong Shao, Jiri Schindler, Steven W. Schlosser...
FOCS
2000
IEEE
14 years 9 hour ago
Cache-Oblivious B-Trees
We present dynamic search-tree data structures that perform well in the setting of a hierarchical memory (including various levels of cache, disk, etc.), but do not depend on the ...
Michael A. Bender, Erik D. Demaine, Martin Farach-...
HIPEAC
2011
Springer
12 years 7 months ago
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
Ahmed Abousamra, Alex K. Jones, Rami G. Melhem
ICMCS
1999
IEEE
145views Multimedia» more  ICMCS 1999»
13 years 12 months ago
A Bandwidth Friendly Search Engine
The Internet plays host to many millions of documents and images and is increasing in size all the time. As a result locating web content is becoming increasingly difficult for us...
Clare Bradford, Ian W. Marshall