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ISCA
2009
IEEE
189views Hardware» more  ISCA 2009»
14 years 2 months ago
Hybrid cache architecture with disparate memory technologies
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ra...
IPPS
2010
IEEE
13 years 5 months ago
Restructuring parallel loops to curb false sharing on multicore architectures
The memory hierarchy of most multicore systems contains one or more levels of cache that is shared among multiple cores. The shared-cache architecture presents many opportunities f...
Santosh Sarangkar, Apan Qasem
IPPS
1998
IEEE
13 years 11 months ago
Memory Hierarchy Management for Iterative Graph Structures
The increasing gap in processor and memory speeds has forced microprocessors to rely on deep cache hierarchies to keep the processors from starving for data. For many applications...
Ibraheem Al-Furaih, Sanjay Ranka
FOCS
2003
IEEE
14 years 24 days ago
The Cost of Cache-Oblivious Searching
This paper gives tight bounds on the cost of cache-oblivious searching. The paper shows that no cache-oblivious search structure can guarantee a search performance of fewer than l...
Michael A. Bender, Gerth Stølting Brodal, R...
WCAE
2006
ACM
14 years 1 months ago
Web memory hierarchy learning and research environment
Learning the various structures and levels of memory hierarchy by means of conventional procedures is a complex subject. A memory hierarchy environment (Web-MHE) was proposed and ...
José Leandro D. Mendes, Luiza M. N. Coutinh...