4809 search results - page 21 / 962 » CajunBot: Architecture and algorithms |
VLSISP
2002
13 years 9 months ago
2002
Abstract. This paper presents a reduced-complexity, fixed-point algorithm and efficient real-time VLSI architectures for multiuser channel estimation, one of the core baseband proc...
ISCAS
2003
IEEE
14 years 3 months ago
2003
IEEE
We present an algorithmic analog-to-digital converter (ADC) architecture for large-scale parallel quantization of internally analog variables in externally digital array processor...
DELTA
2010
IEEE
14 years 3 months ago
2010
IEEE
High level hardware description languages aim to make hardware design more like programming software. These languages are often used to accelerate legacy software algorithms by ...
AHS
2006
IEEE
14 years 4 months ago
2006
IEEE
Domain-specific reconfigurable arrays have shown to provide an efficient trade-off between flexibility of FPGA and performance of ASIC circuit. Nonetheless, the design of these he...
ARITH
1999
IEEE
14 years 2 months ago
1999
IEEE
The IA-64 architecture provides new opportunities and challenges for implementing an improved set of transcendental functions. Using several novel polynomial-based table-driven te...