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ICCD
1999
IEEE
86views Hardware» more  ICCD 1999»
14 years 2 months ago
Evaluation of Computing in Memory Architectures for Digital Image Processing Applications
Continuing improvements in semiconductor density are enabling new classes of System-on-a-Chip architectures that combine extensive processing logic and high-density memory. Many o...
David L. Landis, Paul T. Hulina, Scott Deno, Luke ...
INFOCOM
2000
IEEE
14 years 2 months ago
On the Stability of Input-Buffer Cell Switches with Speed-Up
— We consider cell-based switch architectures, whose internal switching matrix does not provide enough speed to avoid input buffering. These architectures require a scheduling al...
Marco Ajmone Marsan, Emilio Leonardi, Marco Mellia...
RECONFIG
2008
IEEE
122views VLSI» more  RECONFIG 2008»
14 years 4 months ago
Using a CSP Based Programming Model for Reconfigurable Processor Arrays
The growing trend towards adoption of flexible and heterogeneous, parallel computing architectures has increased the challenges faced by the programming community. We propose a me...
Zain-ul-Abdin, Bertil Svensson
EUROPAR
2009
Springer
14 years 4 months ago
Parallel Lattice Basis Reduction Using a Multi-threaded Schnorr-Euchner LLL Algorithm
Abstract. In this paper, we introduce a new parallel variant of the LLL lattice basis reduction algorithm. Our new, multi-threaded algorithm is the first to provide an efficient,...
Werner Backes, Susanne Wetzel
ICT
2004
Springer
165views Communications» more  ICT 2004»
14 years 3 months ago
Algorithms for Distributed Fault Management in Telecommunications Networks
Distributed architectures for network management have been the subject of a large research effort, but distributed algorithms that implement the corresponding functions have been ...
Eric Fabre, Albert Benveniste, Stefan Haar, Claude...