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ICCAD
2008
IEEE
150views Hardware» more  ICCAD 2008»
16 years 3 months ago
Performance estimation and slack matching for pipelined asynchronous architectures with choice
— This paper presents a fast analytical method for estimating the throughput of pipelined asynchronous systems, and then applies that method to develop a fast solution to the pro...
Gennette Gill, Vishal Gupta, Montek Singh
CODES
2006
IEEE
16 years 3 days ago
Layout aware design of mesh based NoC architectures
Design of System-on-Chip (SoC) with regular mesh based Network-on-Chip (NoC) consists of mapping processing cores to routers, and routing of the traffic traces on the topology suc...
Krishnan Srinivasan, Karam S. Chatha
DSD
2005
IEEE
104views Hardware» more  DSD 2005»
15 years 11 months ago
Design of Transport Triggered Architecture Processors for Wireless Encryption
Transport Triggered Architecture (TTA) offers a costeffective trade-off between the size and performance of ASICs and the programmability of general-purpose processors. In this pa...
Panu Hämäläinen, Jari Heikkinen, Ma...
SC
2005
ACM
15 years 11 months ago
Multilevel Parallelism in Computational Chemistry using Common Component Architecture and Global Arrays
The development of complex scientific applications for high-end systems is a challenging task. Addressing complexity of the involved software and algorithms is becoming increasing...
Manojkumar Krishnan, Yuri Alexeev, Theresa L. Wind...
ICS
2005
Tsinghua U.
15 years 11 months ago
Multigrain parallel Delaunay Mesh generation: challenges and opportunities for multithreaded architectures
Given the importance of parallel mesh generation in large-scale scientific applications and the proliferation of multilevel SMTbased architectures, it is imperative to obtain ins...
Christos D. Antonopoulos, Xiaoning Ding, Andrey N....