4809 search results - page 85 / 962 » CajunBot: Architecture and algorithms |
159
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FPL
2009
Springer
15 years 10 months ago
2009
Springer
Clock gating is a power reduction technique that has been used successfully in the custom ASIC domain. Clock and logic signal power are saved by temporarily disabling the clock si...
161
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IFIP
2001
Springer
15 years 10 months ago
2001
Springer
: A new efficient type I architecture for motion estimation in video sequences based on the Full-Search Block-Matching (FSBM) algorithm is proposed in this paper. This architecture...
166
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CSMR
2000
IEEE
15 years 10 months ago
2000
IEEE
This paper presents a technique for recovering the high level design of legacy software systems according to user defined architectural plans. Architectural plans are represented...
143
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ICSE
2007
IEEE-ACM
16 years 6 months ago
2007
IEEE-ACM
Large networks, such as the Internet, pose an ideal medium for solving computationally intensive problems, such as NP-complete problems, yet no well-scaling architecture for Inter...
172
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IPPS
2008
IEEE
16 years 17 days ago
2008
IEEE
The scalable parallel implementation, targeting SMP and/or multicore architectures, of dense linear algebra libraries is analyzed. Using the LU factorization as a case study, it is...