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SIGPLAN
2002
13 years 9 months ago
Write barrier removal by static analysis
We present a new analysis for removing unnecessary write barriers in programs that use generational garbage collection. To our knowledge, this is the first static program analysis...
Karen Zee, Martin C. Rinard
AINA
2009
IEEE
14 years 4 months ago
Modeling Multiprocessor Cache Protocol Impact on MPI Performance
This paper presents a modeling method particularly suited to analyze interactions between Message Passing Interface MPI library execution and distributed cache coherence protocol....
Ghassan Chehaibar, Meriem Zidouni, Radu Mateescu
DATE
2005
IEEE
107views Hardware» more  DATE 2005»
14 years 3 months ago
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique
Complex applications implemented as Systems on Chip (SoCs) demand extensive use of system level modeling and validation. Their implementation gathers a large number of complex IP ...
César A. M. Marcon, Ney Laert Vilar Calazan...
HPCA
1999
IEEE
14 years 2 months ago
A Study of Control Independence in Superscalar Processors
Control independence has been put forward as a significant new source of instruction-level parallelism for future generation processors. However, its performance potential under p...
Eric Rotenberg, Quinn Jacobson, James E. Smith
ICWS
2010
IEEE
13 years 11 months ago
A MVC Framework for Policy-Based Adaptation of Workflow Processes: A Case Study on Confidentiality
Abstract--Most work on adaptive workflows offers insufficient flexibility to enforce complex policies regarding dynamic, evolvable and robust workflows. In addition, many proposed ...
Kristof Geebelen, Eryk Kulikowski, Eddy Truyen, Wo...