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DDECS
2007
IEEE
175views Hardware» more  DDECS 2007»
14 years 1 months ago
Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair
—An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. A commonly used repair strategy is to equip memories with sp...
Philipp Öhler, Sybille Hellebrand, Hans-Joach...
ICPP
2009
IEEE
13 years 5 months ago
Employing Transactional Memory and Helper Threads to Speedup Dijkstra's Algorithm
In this paper we work on the parallelization of the inherently serial Dijkstra's algorithm on modern multicore platforms. Dijkstra's algorithm is a greedy algorithm that ...
Konstantinos Nikas, Nikos Anastopoulos, Georgios I...
JIB
2008
76views more  JIB 2008»
13 years 7 months ago
WebStruct and VisualStruct: web interfaces and visualization for Structure software implemented in a cluster environment
Structure, is a widely used software tool to investigate population genetic structure with multi-locus genotyping data. The software uses an iterative algorithm to group individua...
B. Jayashree, S. Rajgopal, David A. Hoisington, V....
PDP
2010
IEEE
14 years 2 months ago
Experimental Study of Six Different Implementations of Parallel Matrix Multiplication on Heterogeneous Computational Clusters of
—Two strategies of distribution of computations can be used to implement parallel solvers for dense linear algebra problems for Heterogeneous Computational Clusters of Multicore ...
Pedro Alonso, Ravi Reddy, Alexey L. Lastovetsky
SPAA
1998
ACM
13 years 12 months ago
Computation-Centric Memory Models
We present a computation-centric theory of memory models. Unlike traditional processor-centric models, computation-centric models focus on the logical dependencies among instructi...
Matteo Frigo, Victor Luchangco