DDECS 2007 - PDF Preprint Papers

DDECS 2007 Design and Diagnostics of Electronic Circuits and Systems

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DDECS
2007
IEEE

201views Hardware» more DDECS 2007»

Built in Defect Prognosis for Embedded Memories

14 years 5 months ago

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: As scan compression replaces the traditional scan it is important to understand how it works with power. DFT MAX represents one of the two primary scan compression solutions used...

Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskaran...

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Id	Views	Title	Status

1	201	Built in Defect Prognosis for Embedded Memories	claim
2	175	Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair	claim
3	143	An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques	claim
4	143	Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System	claim
5	140	A Framework for Self-Healing Radiation-Tolerant Implementations on Reconfigurable FPGAs	claim
6	139	Debug Patterns for Efficient High-level SystemC Debugging	claim
7	133	Prototyping Generators for On-line Test Vector Generation Based on PSL Properties	claim
8	127	Instance Generation for SAT-based ATPG	claim
9	121	March CRF: an Efficient Test for Complex Read Faults in SRAM Memories	claim
10	121	A Novel Parity Bit Scheme for SBox in AES Circuits	claim
11	106	A Proposal for ASM++ Diagrams	claim
12	105	A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing	claim
13	105	Layout to Logic Defect Analysis for Hierarchical Test Generation	claim
14	103	On Variable Selection in SAT-LP-based Bounded Model Checking of Linear Hybrid Automata	claim
15	102	IP Integration Overhead Analysis in System-on-Chip Video Encoder	claim
16	101	A Low Noise and Low Power CMOS Image Sensor with Pixel-level Correlated Double Sampling	claim
17	93	Manifestation of Precharge Faults in High Speed DRAM Devices	claim
18	90	Test Pattern Generator for Delay Faults	claim
19	86	Design and Analysis of a New Self-Testing Adder which Utilizes Polymorphic Gates	claim
20	80	New Strategies for System-Level Design	claim
21	80	Design Platform for Quick Integration of an Internet Connectivity into System-on-Chips	claim

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