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IPPS
2002
IEEE
14 years 17 days ago
Implementing Associative Search and Responder Resolution
In a paper presented last year at WMPP’01 [Walker01], we described the initial prototype of an associative processor implemented using field-programmable logic devices (FPLDs). ...
Meiduo Wu, Robert A. Walker, Jerry L. Potter
PACT
1999
Springer
13 years 12 months ago
Parallel Implementation of Constraint Solving
Many problems from artificial intelligence can be described as constraint satisfaction problems over finite domains (CSP(FD)), that is, a solution is an assignment of a value to ...
Alvaro Ruiz-Andino, Lourdes Araujo, Fernando S&aac...
FCCM
2005
IEEE
124views VLSI» more  FCCM 2005»
14 years 1 months ago
Parallel Hardware Implementation of Cellular Learning Automata Based Evolutionary Computing (CLA-EC) on FPGA
The CLA-EC is a model obtained by combining the concepts of cellular learning automata and evolutionary algorithms. The parallel structure of the CLA-EC makes it suitable for hard...
Arash Hariri, Reza Rastegar, Morteza Saheb Zamani,...
ICPP
2006
IEEE
14 years 1 months ago
Parallel Information Extraction on Shared Memory Multi-processor System
Text Mining is one of the best solutions for today and the future’s information explosion. With the development of modern processor technologies, it will be a mass market deskto...
Jiulong Shan, Yurong Chen, Qian Diao, Yimin Zhang
SPAA
2005
ACM
14 years 1 months ago
Parallelizing time with polynomial circuits
We study the problem of asymptotically reducing the runtime of serial computations with circuits of polynomial size. We give an algorithmic size-depth tradeoff for parallelizing ...
Ryan Williams