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ISCA
1995
IEEE
110views Hardware» more  ISCA 1995»
13 years 11 months ago
Optimization of Instruction Fetch Mechanisms for High Issue Rates
Recent superscalar processors issue four instructions per cycle. These processors are also powered by highly-parallel superscalar cores. The potential performance can only be expl...
Thomas M. Conte, Kishore N. Menezes, Patrick M. Mi...
JILP
2002
83views more  JILP 2002»
13 years 7 months ago
Using Statistical and Symbolic Simulation for Microprocessor Performance Evaluation
As microprocessor designs continue to evolve, many optimizations reach a point of diminishing returns. We introduce HLS, a hybrid processor simulator which uses statistical models...
Mark Oskin, Frederic T. Chong, Matthew K. Farrens
CODES
2009
IEEE
13 years 11 months ago
TotalProf: a fast and accurate retargetable source code profiler
Profilers play an important role in software/hardware design, optimization, and verification. Various approaches have been proposed to implement profilers. The most widespread app...
Lei Gao, Jia Huang, Jianjiang Ceng, Rainer Leupers...
EDBT
2011
ACM
199views Database» more  EDBT 2011»
12 years 11 months ago
Predicting completion times of batch query workloads using interaction-aware models and simulation
A question that database administrators (DBAs) routinely need to answer is how long a batch query workload will take to complete. This question arises, for example, while planning...
Mumtaz Ahmad, Songyun Duan, Ashraf Aboulnaga, Shiv...
MICRO
2008
IEEE
138views Hardware» more  MICRO 2008»
14 years 2 months ago
Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs
As the number of transistors integrated on a chip continues to increase, a growing challenge is accurately modeling performance in the early stages of processor design. Analytical...
Xi E. Chen, Tor M. Aamodt