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CODES
2008
IEEE
14 years 5 days ago
Model checking SystemC designs using timed automata
SystemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify SystemC designs. In...
Paula Herber, Joachim Fellmuth, Sabine Glesner
GLVLSI
2008
IEEE
157views VLSI» more  GLVLSI 2008»
14 years 4 months ago
Coverage-driven automatic test generation for uml activity diagrams
Due to the increasing complexity of today’s embedded systems, the analysis and validation of such systems is becoming a major challenge. UML is gradually adopted in the embedded...
Mingsong Chen, Prabhat Mishra, Dhrubajyoti Kalita
POPL
2003
ACM
14 years 10 months ago
From symptom to cause: localizing errors in counterexample traces
There is significant room for improving users' experiences with model checking tools. An error trace produced by a model checker can be lengthy and is indicative of a symptom...
Thomas Ball, Mayur Naik, Sriram K. Rajamani
ECBS
2005
IEEE
160views Hardware» more  ECBS 2005»
14 years 4 months ago
Traceability-Driven Model Refinement for Test Case Generation
Testing complex Computer-Based Systems is not only a demanding but a very critical task. Therefore the use of models for generating test data is an important goal. Tool support du...
Matthias Riebisch, Michael Hübner
SIGSOFT
2007
ACM
14 years 11 months ago
CTG: a connectivity trace generator for testing the performance of opportunistic mobile systems
The testing of the performance of opportunistic communication protocols and applications is usually done through simulation as i) deployments are expensive and should be left to t...
Roberta Calegari, Mirco Musolesi, Franco Raimondi,...