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DFT
2005
IEEE
72views VLSI» more  DFT 2005»
14 years 10 days ago
Soft Error Modeling and Protection for Sequential Elements
Sequential elements, flip-flops, latches, and memory cells, are the most vulnerable components to soft errors. Since state-of-the-art designs contain millions of bistables, it i...
Hossein Asadi, Mehdi Baradaran Tahoori
VLSID
2000
IEEE
90views VLSI» more  VLSID 2000»
13 years 11 months ago
Performance Analysis of Systems with Multi-Channel Communication Architectures
This paper presents a novel system performance analysis technique to support the design of custom communication architectures for System-on-Chip ICs. Our technique fills a gap in...
Kanishka Lahiri, Sujit Dey, Anand Raghunathan
ICASSP
2011
IEEE
12 years 10 months ago
An analytic approach in joint delay and Doppler estimation using copula
In this paper, a new method is proposed for delay and Doppler estimation using copula theory. Copula analysis helps to explore the underlying inter-dependence between the desired ...
Mohammad Hossein Gholizadeh, Hamidreza Amindavar
UAI
2001
13 years 8 months ago
Iterative Markov Chain Monte Carlo Computation of Reference Priors and Minimax Risk
We present an iterative Markov chain Monte Carlo algorithm for computing reference priors and minimax risk for general parametric families. Our approach uses MCMC techniques based...
John D. Lafferty, Larry A. Wasserman
DAC
2005
ACM
13 years 8 months ago
Smart diagnostics for configurable processor verification
This paper describes a novel technique called Embedded Test-bench Control (ETC), extensively used in the verification of Tensilica’s latest configurable processor. Conventional ...
Sadik Ezer, Scott Johnson