Performance Analysis of Systems with Multi-Channel Communication Architectures

This paper presents a novel system performance analysis technique to support the design of custom communication architectures for System-on-Chip ICs. Our technique fills a gap in existing techniques for system-level performance analysis, which are either too slow to use in an iterative communication architecture design framework (e.g., simulation of the complete system), or are not accurate enough to drive the design of the communication architecture (e.g., techniques that perform a “static” analysis of the system performance). Our technique is based on a hybrid, trace-based performance analysis methodology where an initial co-simulation of the system is performed with the communication described in an abstract man., as events or abstract data transfers). An abstract set of traces are extracted from the initial co-simulation that contain necessary and sufficient information about the computations and communications of the system components. The system designer then specifies a ...

• Type: Conference
• Year: 2000
• Where: VLSID
• Authors: Kanishka Lahiri, Sujit Dey, Anand Raghunathan
• Keywords: Communication Architecture, Performance Analysis, Performance Analysis Technique, VLSI, VLSID 2000