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ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
14 years 13 days ago
Re-architecting DRAM memory systems with monolithically integrated silicon photonics
The performance of future manycore processors will only scale with the number of integrated cores if there is a corresponding increase in memory bandwidth. Projected scaling of el...
Scott Beamer, Chen Sun, Yong-Jin Kwon, Ajay Joshi,...
INFOCOM
2002
IEEE
14 years 8 days ago
Design of Wavelength Converting Switches for Optical Burst Switching
— Optical Burst Switching (OBS) is an experimental network technology that enables the construction of very high capacity routers, using optical data paths and electronic control...
Jeyashankher Ramamirtham, Jonathan S. Turner
DELTA
2006
IEEE
13 years 11 months ago
Implementation of Four Real-Time Software Defined Receivers and a Space-Time Decoder using Xilinx Virtex 2 Pro Field Programmabl
This paper describes the concept, architecture, development and demonstration of a real time, high performance, software defined 4-receiver system and a space time decoder to be i...
Peter J. Green, Desmond P. Taylor
WSC
2007
13 years 9 months ago
A model for contact center analysis and simulation
In this paper we depart from a set of simple assumptions regarding the behavior of a pool of customers associated with an enterprise’s contact center. We assume that the pool of...
Juan M. Huerta
MOBICOM
2010
ACM
13 years 7 months ago
CTRL: a self-organizing femtocell management architecture for co-channel deployment
Femtocell technology has been drawing considerable attention as a cost-effective means of improving cellular coverage and capacity. However, under co-channel deployment, femtocell...
Ji-Hoon Yun, Kang G. Shin