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ICPP
1996
IEEE
13 years 11 months ago
Scheduling of Wavefront Parallelism on Scalable Shared-memory Multiprocessors
Tiling exploits temporal reuse carried by an outer loop of a loop nest to enhance cache locality. Loop skewing is typically required to make tiling legal. This restricts parallelis...
Naraig Manjikian, Tarek S. Abdelrahman
SADM
2011
13 years 2 months ago
Trellis display for modeling data from designed experiments
Abstract: Visualizing data by graphing a response against certain factors, and conditioning on other factors, has arisen independently in many contexts. One is the interaction plot...
Montserrat Fuentes, Bowei Xi, William S. Cleveland
MICRO
2009
IEEE
191views Hardware» more  MICRO 2009»
14 years 2 months ago
Pseudo-LIFO: the foundation of a new family of replacement policies for last-level caches
Cache blocks often exhibit a small number of uses during their life time in the last-level cache. Past research has exploited this property in two different ways. First, replacem...
Mainak Chaudhuri
VRST
2006
ACM
14 years 1 months ago
Hand-held virtual reality: a feasibility study
Hand-held computing devices are ubiquitous and have become part of our lives these days. Moreover, hand-held devices are also increasingly being equipped with special sensors and ...
Jane Hwang, Jaehoon Jung, Gerard Jounghyun Kim
IEEEPACT
2005
IEEE
14 years 1 months ago
Trace Cache Sampling Filter
This paper presents a new technique for efficient usage of small trace caches. A trace cache can significantly increase the performance of wide out-oforder processors, but to be e...
Michael Behar, Avi Mendelson, Avinoam Kolodny