Tiling exploits temporal reuse carried by an outer loop of a loop nest to enhance cache locality. Loop skewing is typically required to make tiling legal. This restricts parallelis...
Abstract: Visualizing data by graphing a response against certain factors, and conditioning on other factors, has arisen independently in many contexts. One is the interaction plot...
Montserrat Fuentes, Bowei Xi, William S. Cleveland
Cache blocks often exhibit a small number of uses during their life time in the last-level cache. Past research has exploited this property in two different ways. First, replacem...
Hand-held computing devices are ubiquitous and have become part of our lives these days. Moreover, hand-held devices are also increasingly being equipped with special sensors and ...
This paper presents a new technique for efficient usage of small trace caches. A trace cache can significantly increase the performance of wide out-oforder processors, but to be e...