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ISCA
2009
IEEE
189views Hardware» more  ISCA 2009»
14 years 2 months ago
Hybrid cache architecture with disparate memory technologies
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ra...
SLIP
2003
ACM
14 years 23 days ago
A hierarchical three-way interconnect architecture for hexagonal processors
The problem of interconnect architecture arises when an array of processors needs to be integrated on one chip. With the deep sub-micron technology, devices become cheap while wir...
Feng Zhou, Esther Y. Cheng, Bo Yao, Chung-Kuan Che...
IPPS
2006
IEEE
14 years 1 months ago
Implementation of a programmable array processor architecture for approximate string matching algorithms on FPGAs
Approximate string matching problem is a common and often repeated task in information retrieval and bioinformatics. This paper proposes a generic design of a programmable array p...
Panagiotis D. Michailidis, Konstantinos G. Margari...
ISCAS
2008
IEEE
101views Hardware» more  ISCAS 2008»
14 years 1 months ago
High-performance ASIC implementations of the 128-bit block cipher CLEFIA
— In the present paper, we introduce high-performance hardware architectures for the 128-bit block cipher CLEFIA and evaluate their ASIC performances in comparison with the ISO/I...
Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Ak...
ACSAC
2006
IEEE
14 years 1 months ago
Delegate: A Proxy Based Architecture for Secure Website Access from an Untrusted Machine
Performing sensitive online transactions using computers found in cybercaf´es and public libraries is risky. The untrusted nature of these machines creates a target rich environm...
Ravi Chandra Jammalamadaka, Timothy W. van der Hor...