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DAC
1996
ACM
14 years 24 days ago
Integrating Formal Verification Methods with A Conventional Project Design Flow
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional pr...
Ásgeir Th. Eiríksson
FMICS
2010
Springer
13 years 9 months ago
Embedded Network Protocols for Mobile Devices
Embedded networks for chip-to-chip networks are emerging as communication infrastructure in mobile devices. We present three novel embedded network protocols: a sliding window prot...
Despo Galataki, Andrei Radulescu, Kees Verstoep, W...
FM
2001
Springer
118views Formal Methods» more  FM 2001»
14 years 1 months ago
Avoiding State Explosion for Distributed Systems with Timestamps
This paper describes a reduction technique which is very useful against the state explosion problem which occurs when model checking many distributed systems. Timestamps are often ...
Fabrice Derepas, Paul Gastin, David Plainfoss&eacu...
ICSR
2011
Springer
13 years 3 days ago
Software Reuse and Safety
With the move to distributed, component based systems involving reuse of components and services, emergent, system-wide properties, including safety and security in particular, are...
William B. Frakes, John M. Favaro
HVC
2007
Springer
106views Hardware» more  HVC 2007»
14 years 16 days ago
Exploiting Shared Structure in Software Verification Conditions
Abstract. Despite many advances, today's software model checkers and extended static checkers still do not scale well to large code bases, when verifying properties that depen...
Domagoj Babic, Alan J. Hu