Sciweavers

794 search results - page 129 / 159
» Challenges in Parallel Graph Processing
Sort
View
ASPDAC
2004
ACM
109views Hardware» more  ASPDAC 2004»
14 years 2 months ago
Design methodology for IRA codes
Channel coding is an important building block in communication systems since it ensures the quality of service. Irregular repeat-accumulate (IRA) codes belong to the class of Low-...
Frank Kienle, Norbert Wehn
CISIS
2010
IEEE
14 years 5 days ago
Automatic Offloading of C++ for the Cell BE Processor: A Case Study Using Offload
Offload C++ is an extended version of the C++ language, together with a compiler and runtime system, for automatically offloading general-purpose C++ code to run on the Synergistic...
Alastair F. Donaldson, Uwe Dolinsky, Andrew Richar...
IJHPCA
2006
117views more  IJHPCA 2006»
13 years 8 months ago
Recent Developments in Gridsolve
The purpose of GridSolve is to create the middleware necessary to provide a seamless bridge between the simple, standard programming interfaces and desktop systems that dominate t...
Asim YarKhan, Keith Seymour, Kiran Sagi, Zhiao Shi...
CORR
2007
Springer
154views Education» more  CORR 2007»
13 years 8 months ago
Application of a design space exploration tool to enhance interleaver generation
This paper presents a methodology to efficiently explore the design space of communication adapters. In most digital signal processing (DSP) applications, the overall performance ...
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eri...
IEEEPACT
2008
IEEE
14 years 3 months ago
Multitasking workload scheduling on flexible-core chip multiprocessors
While technology trends have ushered in the age of chip multiprocessors (CMP) and enabled designers to place an increasing number of cores on chip, a fundamental question is what ...
Divya Gulati, Changkyu Kim, Simha Sethumadhavan, S...