658 search results - page 30 / 132 » Challenges in Physical Chip Design |
RTAS
2008
IEEE
14 years 3 months ago
2008
IEEE
This paper provides four contributions to the study of optimization techniques for component-based distributed realtime and embedded (DRE) systems. First, we describe key challeng...
GLOBECOM
2009
IEEE
13 years 12 months ago
2009
IEEE
—In wireless networks, mutual interference prevents wireless devices from correctly receiving packages from others and becomes one of the challenges in the design of protocols fo...
CISIS
2008
IEEE
14 years 3 months ago
2008
IEEE
As the end of Moores-law is on the horizon, power becomes a limiting factor to continuous increases in performance gains for single-core processors. Processor engineers have shifte...
ICCD
2011
IEEE
12 years 8 months ago
2011
IEEE
—A key challenge in chip multiprocessor (CMP) design is to optimize the performance within a power budget limited by the CMP’s cooling, packaging, and power supply capacities. ...
MSE
2005
IEEE
14 years 2 months ago
2005
IEEE
The reusing of Intellectual Property cores has been an alternative to the increasing gap between design productivity and chip complexity of emerging System-on-chip (SoC) designs. ...