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» Challenges in Physical Chip Design
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LCTRTS
2010
Springer
13 years 6 months ago
Compiler directed network-on-chip reliability enhancement for chip multiprocessors
Chip multiprocessors (CMPs) are expected to be the building blocks for future computer systems. While architecting these emerging CMPs is a challenging problem on its own, program...
Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin,...
ISPD
2003
ACM
88views Hardware» more  ISPD 2003»
14 years 1 months ago
Porosity aware buffered steiner tree construction
— In order to achieve timing closure on increasingly complex IC designs, buffer insertion needs to be performed on thousands of nets within an integrated physical synthesis syste...
Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jia...
CIDR
2007
173views Algorithms» more  CIDR 2007»
13 years 10 months ago
Database Servers on Chip Multiprocessors: Limitations and Opportunities
Prior research shows that database system performance is dominated by off-chip data stalls, resulting in a concerted effort to bring data into on-chip caches. At the same time, hi...
Nikos Hardavellas, Ippokratis Pandis, Ryan Johnson...
NOCS
2007
IEEE
14 years 3 months ago
Towards Open Network-on-Chip Benchmarks
Measuring and comparing performance, cost, and other features of advanced communication architectures for complex multi core/multiprocessor systems on chip is a significant challe...
Cristian Grecu, André Ivanov, Partha Pratim...
SIPS
2007
IEEE
14 years 3 months ago
Dynamic Channel Flow Control of Networks-on-Chip Systems for High Buffer Efficiency
System-on-Chip (SoC) designs become more complex nowadays. The communication between each processing element often suffers challenges due to the wiring problem. Networks-on-Chip (...
Sung-Tze Wu, Chih-Hao Chao, I-Chyn Wey, An-Yeu Wu