658 search results - page 67 / 132 » Challenges in Physical Chip Design |
TC
2011
13 years 3 months ago
2011
—Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Since a large fraction of chip area is devoted to on-...
VLSI
2007
Springer
14 years 2 months ago
2007
Springer
In this paper, we present the way of fast and accurate estimation of software energy consumption in off-the-shelf processor using IPI(Inter-Prefetch Interval) energy model. In ou...
CAL
2007
13 years 8 months ago
2007
—The design of scalable and reliable interconnection networks for multicore chips (NoCs) introduces new design constraints like power consumption, area, and ultra low latencies. ...
NOCS
2009
IEEE
14 years 3 months ago
2009
IEEE
With the advent of Networks-on-Chip (NoCs), the interest for mesochronous synchronizers is again on the rise due to the intricacies of skew-controlled chip-wide clock tree distrib...
WACV
2002
IEEE
14 years 1 months ago
2002
IEEE
This paper describes design and implementation of a vision based platform for automated refueling tasks. The platform is an autonomous docking system in principle, with the specif...