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» Challenges in Physical Chip Design
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ISCA
2012
IEEE
191views Hardware» more  ISCA 2012»
11 years 11 months ago
VRSync: Characterizing and eliminating synchronization-induced voltage emergencies in many-core processors
Power consumption is a primary concern for microprocessor designers. Lowering the supply voltage of processors is one of the most effective techniques for improving their energy e...
Timothy N. Miller, Renji Thomas, Xiang Pan, Radu T...
VEE
2012
ACM
234views Virtualization» more  VEE 2012»
12 years 4 months ago
REEact: a customizable virtual execution manager for multicore platforms
With the shift to many-core chip multiprocessors (CMPs), a critical issue is how to effectively coordinate and manage the execution of applications and hardware resources to overc...
Wei Wang, Tanima Dey, Ryan W. Moore, Mahmut Aktaso...
WSC
1998
13 years 10 months ago
Multimodels and Dynamic Structure Models: An Integration of DSDE/DEVS and OOPM
Constructing models of systems that change their structure over time has proved to be a challenging problem, with several proposed solutions. We present two of these approaches an...
Fernando J. Barros, Bernard P. Zeigler, Paul A. Fi...
TMC
2008
110views more  TMC 2008»
13 years 8 months ago
Understanding the Impact of Interference on Collaborative Relays
Collaborative relays achieve the benefits of spatial diversity without requiring physical antenna arrays at end devices. While many studies have demonstrated its effectiveness in a...
Yan Zhu, Haitao Zheng
ICRA
2010
IEEE
144views Robotics» more  ICRA 2010»
13 years 6 months ago
Deformable robot motion planning in a reduced-dimension configuration space
Abstract-- Motion planning of deformable objects is challenging due to the high degrees-of-freedom inherent in deformation as well as the computational cost of producing physically...
Arthur Mahoney, Joshua Bross, David Johnson