Sciweavers

658 search results - page 72 / 132
» Challenges in Physical Chip Design
Sort
View
CHES
2011
Springer
240views Cryptology» more  CHES 2011»
12 years 8 months ago
Lightweight and Secure PUF Key Storage Using Limits of Machine Learning
A lightweight and secure key storage scheme using silicon Physical Unclonable Functions (PUFs) is described. To derive stable PUF bits from chip manufacturing variations, a lightwe...
Meng-Day (Mandel) Yu, David M'Raïhi, Richard ...
ICPPW
2009
IEEE
14 years 3 months ago
Hardware Microkernels for Heterogeneous Manycore Systems
Abstract— The migration away from power-hungry, speculative execution procesors towards manycore architectures is good news for the embedded and real-time systems community. Comm...
Jason Agron, David L. Andrews
TVLSI
2008
152views more  TVLSI 2008»
13 years 8 months ago
MMV: A Metamodeling Based Microprocessor Validation Environment
With increasing levels of integration of multiple processing cores and new features to support software functionality, recent generations of microprocessors face difficult validati...
Deepak Mathaikutty, Sreekumar V. Kodakara, Ajit Di...
APCHI
2004
IEEE
14 years 17 days ago
Supporting Work Activities in Healthcare by Mobile Electronic Patient Records
Abstract. Supporting work activities in healthcare is highly complex and challenging. This paper outlines the findings from a usability study of a commercial PC based electronic pa...
Jesper Kjeldskov, Mikael B. Skov
DAC
2004
ACM
14 years 9 months ago
High level cache simulation for heterogeneous multiprocessors
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Don...