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» Challenges in Physical Chip Design
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CSCW
2004
ACM
13 years 8 months ago
People-to-People-to-Geographical-Places: The P3 Framework for Location-Based Community Systems
Abstract. In this paper we examine an emerging class of systems that link People-to-People-toGeographical-Places; we call these P3-Systems. Through analyzing the literature, we hav...
Quentin Jones, Sukeshini A. Grandhi, Loren G. Terv...
BICA
2010
13 years 3 months ago
Explanatory Aspirations and the Scandal of Cognitive Neuroscience
In this position paper we argue that BICA must simultaneously be compatible with the explanation of human cognition and support the human design of artificial cognitive systems. Mo...
Ross Gayler, Simon D. Levy, Rens Bod
DAC
2003
ACM
14 years 9 months ago
Pushing ASIC performance in a power envelope
Power dissipation is becoming the most challenging design constraint in nanometer technologies. Among various design implementation schemes, standard cell ASICs offer the best pow...
Ruchir Puri, Leon Stok, John M. Cohn, David S. Kun...
ICS
2010
Tsinghua U.
14 years 6 months ago
Cache Replacement Policies for Multicore Processors
Almost all of the modern computers use multiple cores, and the number of cores is expected to increase as hardware prices go down, and Moore's law fails to hold. Most of the ...
Avinatan Hassidim
SC
2009
ACM
14 years 3 months ago
Future scaling of processor-memory interfaces
Continuous evolution in process technology brings energyefficiency and reliability challenges, which are harder for memory system designs since chip multiprocessors demand high ba...
Jung Ho Ahn, Norman P. Jouppi, Christos Kozyrakis,...