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DSD
2006
IEEE
131views Hardware» more  DSD 2006»
14 years 14 days ago
Designing Efficient Irregular Networks for Heterogeneous Systems-on-Chip
Abstract-- Networks-on-Chip will serve as the central integration platform in future complex SoC designs, composed of a large number of heterogeneous processing resources. Most res...
Christian Neeb, Norbert Wehn
JSSPP
2005
Springer
14 years 2 months ago
Modeling User Runtime Estimates
User estimates of job runtimes have emerged as an important component of the workload on parallel machines, and can have a significant impact on how a scheduler treats different ...
Dan Tsafrir, Yoav Etsion, Dror G. Feitelson
ICS
2001
Tsinghua U.
14 years 1 months ago
Cache performance for multimedia applications
The caching behavior of multimedia applications has been described as having high instruction reference locality within small loops, very large working sets, and poor data cache p...
Nathan T. Slingerland, Alan Jay Smith
CF
2004
ACM
14 years 2 months ago
Predictable performance in SMT processors
Current instruction fetch policies in SMT processors are oriented towards optimization of overall throughput and/or fairness. However, they provide no control over how individual ...
Francisco J. Cazorla, Peter M. W. Knijnenburg, Riz...
IPPS
1998
IEEE
14 years 1 months ago
Performance Sensitivity of Space Sharing Processor Scheduling in Distributed-Memory Multicomputers
- Processor scheduling in distributed-memory systems has received considerable attention in recent years. Several commercial distributed-memory systems use spacesharing processor s...
Sivarama P. Dandamudi, Hai Yu