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ASPLOS
2009
ACM
14 years 8 months ago
Architectural support for SWAR text processing with parallel bit streams: the inductive doubling principle
Parallel bit stream algorithms exploit the SWAR (SIMD within a register) capabilities of commodity processors in high-performance text processing applications such as UTF8 to UTF-...
Robert D. Cameron, Dan Lin
SAMOS
2009
Springer
14 years 2 months ago
Runtime Adaptive Extensible Embedded Processors - A Survey
Current generation embedded applications demand the computation engine to offer high performance similar to custom hardware circuits while preserving the flexibility of software s...
Huynh Phung Huynh, Tulika Mitra
ARCS
2004
Springer
14 years 27 days ago
Cryptonite - A Programmable Crypto Processor Architecture for High-Bandwidth Applications
Cryptographic methods are widely used within networking and digital rights management. Numerous algorithms exist, e.g. spanning VPNs or distributing sensitive data over a shared ne...
Rainer Buchty, Nevin Heintze, Dino Oliva
DATE
2006
IEEE
118views Hardware» more  DATE 2006»
14 years 1 months ago
Design and implementation of a modular and portable IEEE 754 compliant floating-point unit
Multimedia and communication algorithms from embedded system domain often make extensive use of floating-point arithmetic. Due to the complexity and expense of the floating-poin...
Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Hei...
ASAP
2000
IEEE
102views Hardware» more  ASAP 2000»
13 years 11 months ago
A Theory for Software-Hardware Co-Scheduling for ASIPs and Embedded Processors
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded proces...
Ramaswamy Govindarajan, Erik R. Altman, Guang R. G...