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144
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GLOBECOM
2006
IEEE
15 years 10 months ago
Investigation of Error Floors of Structured Low-Density Parity-Check Codes by Hardware Emulation
Abstract−Several high performance LDPC codes have paritycheck matrices composed of permutation submatrices. We design a parallel-serial architecture to map the decoder of any str...
Zhengya Zhang, Lara Dolecek, Borivoje Nikolic, Ven...
119
Voted
FPGA
2004
ACM
117views FPGA» more  FPGA 2004»
15 years 10 months ago
A magnetoelectronic macrocell employing reconfigurable threshold logic
In this paper, we introduce a reconfigurable fabric based around a new class of circuit element: the hybrid Hall effect (HHE) magnetoelectronic device. Because they incorporate a ...
Steve Ferrera, Nicholas P. Carter
TIT
2011
209views more  TIT 2011»
14 years 11 months ago
Belief Propagation and LP Relaxation for Weighted Matching in General Graphs
Loopy belief propagation has been employed in a wide variety of applications with great empirical success, but it comes with few theoretical guarantees. In this paper we analyze t...
Sujay Sanghavi, Dmitry M. Malioutov, Alan S. Wills...
204
Voted
ICCD
2008
IEEE
420views Hardware» more  ICCD 2008»
16 years 1 months ago
Frequency and voltage planning for multi-core processors under thermal constraints
— Clock frequency and transistor density increases have resulted in elevated chip temperatures. In order to meet temperature constraints while still exploiting the performance op...
Michael Kadin, Sherief Reda
PARELEC
2006
IEEE
15 years 10 months ago
Application-Driven Development of Concurrent Packet Processing Platforms
We have developed an application-driven methodology for implementing parallel and heterogeneous programmable platforms. We deploy our flow for network access platforms where we h...
Christian Sauer, Matthias Gries, Jörg-Christi...