535 search results - page 34 / 107 » Checking Computations in Polylogarithmic Time |
VLSID
2003
IEEE
14 years 8 months ago
2003
IEEE
Most verification tools and methodologies such as model checking, equivalence checking, hardware verification, software verification, and hardware-software coverification often fl...
DLT
2009
13 years 5 months ago
2009
Abstract. Temporal logics are a well investigated formalism for the specification and verification of reactive systems. Using formal verification techniques, we can ensure the corr...
CORR
2010
Springer
13 years 7 months ago
2010
Springer
The transition from single-core to multi-core processors has made multi-threaded software an important subject in computer aided verification. Here, we describe and evaluate an ex...
ICFEM
2009
Springer
13 years 5 months ago
2009
Springer
In this paper we continue the study of a strict extension of the Computation Tree Logic, called graded-CTL, recently introduced by the same authors. This new logic augments the sta...
FMCAD
2008
Springer
13 years 9 months ago
2008
Springer
Parameterized model checking refers to any method that extends traditional, finite-state model checking to handle systems arbitrary number of processes. One popular approach to thi...