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HPCC
2009
Springer
14 years 5 days ago
A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures
—The potential for destructive interference between running processes is increased as Chip Multiprocessors (CMPs) share more on-chip resources. We believe that understanding the ...
Magnus Jahre, Marius Grannæs, Lasse Natvig
HPCA
2000
IEEE
13 years 12 months ago
Dynamic Cluster Assignment Mechanisms
Clustered microarchitectures are an effective approach to reducing the penalties caused by wire delays inside a chip. Current superscalar processors have in fact a two-cluster mic...
Ramon Canal, Joan-Manuel Parcerisa, Antonio Gonz&a...
ECRTS
1999
IEEE
13 years 12 months ago
Distributed real-time task monitoring in the safety-critical system Melody
Safety-critical systems typically operate in unpredictable environments. Requirements for safety and reliability are in conflict with those for real-time responsiveness. Due to un...
Horst F. Wedde, Jon A. Lind, Guido Seghert
ICDCS
2009
IEEE
14 years 4 months ago
Reducing Disk I/O Performance Sensitivity for Large Numbers of Sequential Streams
Retrieving sequential rich media content from modern commodity disks is a challenging task. As disk capacity increases, there is a need to increase the number of streams that are ...
George Panagiotakis, Michail Flouris, Angelos Bila...
RTSS
2007
IEEE
14 years 1 months ago
Energy-Aware Scheduling of Real-Time Tasks in Wireless Networked Embedded Systems
Recent technological advances have opened up several distributed real-time applications involving battery-driven embedded devices with local processing and wireless communication ...
G. Sudha Anil Kumar, G. Manimaran